1. Field of the Invention
The invention relates to a method of manufacturing semiconductor devices whereby a Ti layer and a TiN layer are deposited on integrated circuit substrates in a single PVD deposition chamber without using either a collimator or a shutter.
2. Statement of the Problem
In modern integrated circuit (xe2x80x9cICxe2x80x9d) technology, a metallization comprising a Ti layer, a TiN layer and a top conductive layer is often provided on a surface of a semiconductor body. The Ti layer serves to obtain a good adhesion and a low contact resistance between the metallization and the semiconductor body. When a layer of Al or Al alloyed with a few percent of Si or Cu is used as the conductive top layer, the TiN layer serves as a barrier to prevent chemical reactions of the Al with the Ti layer and the semiconductor material situated underneath the barrier layer. When W is used as a conductive top layer, deposited by means of a usual chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) process for which WF6 is used, the TiN serves as a barrier to prevent chemical reactions between Ti and F which is formed during such a CVD process. Thus, a typical IC fabrication process includes forming a stack of layers represented by Al/TiN/Ti/SiOx/Si or W/TiN/Ti/SiOx/Si.
In addition, anti-reflective coatings are frequently used in semiconductor processing to reduce light reflectance on the surface of metallic layers. Aluminum is widely used as a metallization layer material due to its low melting point, high conductivity and low cost. However, one drawback of Al is that the surface of Al is highly reflective. This high surface reflectivity greatly hampers the imaging process necessary for lithography. During a lithographic process, a photoresist layer must be deposited on the Al surface based on a photographical pattern previously formed in a photo-imaging mask. The high reflectivity from the surface of Al renders this photographic transfer process extremely difficult. To reduce the high reflectivity of Al, an anti-reflective coating (xe2x80x9cARCxe2x80x9d) layer of TiN can be deposited on the surface of Al. The TiN layer appears as a brown or golden tint which significantly reduces the reflectivity of Al from near 100% to approximately 20% at the wavelengths of visible light. This ARC deposition process is a very important step in semiconductor processes whenever aluminum or other highly reflective metal layer is used.
Thus, a typical stack arrangement on an IC semiconductor substrate may include a Ti contact layer on the semiconductor surface, a TiN barrier layer, an Al interconnect layer, and a TiN ARC layer for the purpose of reducing optical reflection. Such a stack may be represented by TiN/Al/TiN/Ti/SiOx/Si.
Various plasma vapor deposition (xe2x80x9cPVDxe2x80x9d) sputtering techniques known in the art for depositing TiN/Ti stacks may be categorized as either nitrided mode (xe2x80x9cNMxe2x80x9d) or non-nitrided mode (xe2x80x9cNNMxe2x80x9d) techniques. In the NM (nitrided mode), typically a titanium target is placed in a sputter chamber, and the TiN layers are deposited by sputtering titanium with a sputter gas in the presence of nitrogen. For example, in a typical PVD technique, argon (xe2x80x9cArxe2x80x9d) gas supports a plasma used in plasma sputtering while the N2-gas reacts with the sputtered Ti to form TiN. In a NM technique, the titanium target is inundated with nitrogen atoms, becoming xe2x80x9cnitridedxe2x80x9d, such that a coating of TiN forms on the surface of the titanium target. This decreases the overall deposition rate of the desired layer of TiN onto the IC substrate because the nitrogen in the titanium target interferes with the sputtering of titanium. Another disadvantage is that the titanium target used to deposit TiN cannot then be used to deposit Ti. As a result, separate deposition chambers are required for each stage involving deposition of Ti and TiN. For example, in a conventional process to make a TiN/Al/TiN/Ti/SiOx stack, a PVD four-chamber cluster system includes Ti targets in three chambers and an Al target in one chamber. The Ti contact layer is deposited by maintaining a partial pressure of Ar gas in the respective chamber, while the TiN layers are deposited by maintaining a partial pressure of Ar and N2 gases in the respective process chambers.
It is known in the art to use a shutter that allows deposition of Ti and TiN in the same deposition chamber. A Ti layer is first deposited using a Ti target. Then, a TiN layer is deposited on the Ti layer using the same Ti target in a NM. During TiN deposition in NM, the Ti target becomes nitrided. Before depositing the Ti layer on the next wafer, the shutter is inserted between the target and the wafer, and the target is sputtered in the absence of nitrogen gas to sputter away the nitrided parts. The target is thereby returned to its clean, metallic state and is ready for the sputtering of pure Ti.
To reduce the inefficiency of using a shutter or separate chambers for Ti and TiN deposition, modifications in the sputtering sequence have been suggested in the prior art. U.S. Pat. No. 5,858,183, issued Jan. 12, 1999, to Wolters et al., and U.S. Pat. No. 5,738,917, issued Apr. 14, 1998, to Besser et al, disclose NM techniques in which an extra Ti layer is deposited on a TiN layer before deposition of the aluminum layer, resulting in a Al/Ti/TiN/Ti/substrate stack. During the deposition of a TiN layer in the nitrided mode (NM), a plasma is generated in a gas mixture comprising Ar and N2 near the Ti target. A nitrided layer comprising nitrogen is created thereby on the Ti target during this deposition step. During an extra process step, the titanium target is sputtered in the absence N2 gas, resulting in deposition of an extra Ti layer containing nitrogen atoms. The extra sputtering step is intended to sputter away the nitrogen in the nitrided titanium target, returning it to a pure Ti, or metallic, state. If sufficiently cleaned, the Ti target is ready to deposit only Ti atoms on the surface of the next wafer being processed. This approach reduces the number of chambers being used. This known method has the disadvantage, however, that the extra layer comprising free Ti is deposited on top of the TiN layer. If a conductive top layer of Al or Al alloyed with a few percents of Si or Cu is provided thereon, the Al and free Ti atoms react with one another, forming compounds with a comparatively high electrical resistance. As a result, the conductive Al layer must then be provided to a comparatively large thickness in order to ensure that conductor tracks having a comparatively low resistance can be formed in the layer structure thus created. If a W layer is deposited on the extra Ti layer comprising free Ti by means of a usual CVD process in which WF6 is used, then the free Ti reacts with F formed during such a CVD process. This leads to the formation of TiF3, to which W has a bad adhesion.
A similar approach is disclosed in U.S. Pat. No. 5,607,776, issued Mar. 4, 1997 to Mueller et al., which teaches deposition of an extra Ti layer onto a TiN-ARC layer, resulting in a Ti/TiN/Al/TiN/Ti/substrate stack. Even though Mueller et al. teach a thin layer of Ti, the extra Ti layer is very reflective and reduces the effect of the TiN-ARC layer. Furthermore, these conventional methods have the disadvantage of adding a process step to an already slow NM technique.
As IC structures have become more compact, the need for low resistance metal interconnects between these structures has increased. Tungsten deposited by CVD and aluminum doped with Cu or Si have been used recently in the industry to provide these interconnections. In the up-to-date semiconductor device, interconnection holes (contact holes or vias), which are provided in the interlayer dielectric (xe2x80x9cILDxe2x80x9d) layer between the circuit elements and the wiring, have become narrower and relatively deeper, and it is difficult to form tungsten or Al alloy in contact holes by a sputtering process. As a result, low pressure chemical vapor deposition (xe2x80x9cLPCVDxe2x80x9d) techniques having good step coverage have been adopted for filling contact holes with a tungsten (W) plug. A W layer, however, tends to peel off a substrate because of its low adhesive strength to ILDs. Further, if W is directly grown on Si, then precursor WF6 gas and Si, the typical semiconductor substrate, often react with each other to destroy the circuit elements. Therefore, as with Al metallization layers, instead of forming a W film or plug on the substrate directly, a Ti liner layer is formed at the bottom of a via, a TiN barrier layer is formed on the Ti, and then W is grown thereon to fill the via. In this case, in order to completely prevent destruction of the IC elements, at least 10 nm of the TiN film is typically necessary on the bottom of a via or contact hole.
Conventional sputtering of Ti and TiN provides satisfactory results when used on a planar surface or when used to coat the sidewalks and bottom of an aperture (or via), where the ratio of the height of the aperture to its width, hereinafter the xe2x80x9caspect ratioxe2x80x9d (xe2x80x9cARxe2x80x9d) of the via, is less than 1:1. However, as the aspect ratio of the via increases, conventional sputtering does not provide acceptable results. Specifically, far less material is deposited at the bottom portions of the via or hole than at the top, since the walls xe2x80x9cshadowxe2x80x9d the lower exposed surface. The deposited material at the upper surfaces increasingly accentuates the shadowing effect, thereby prematurely closing the upper section of the via and preventing effective fill of the lower section. For example, with a conventional sputter method, bottom coverage is only about 5% in a via having an AR of 5:1.
Accordingly, it has been a goal of manufacturers of sputtering systems to provide means for imparting greater directionality to the ejected target atoms that reach the wafer. Ideally, for filling vias and grooves, sputtered atoms should arrive at an angle which is normal to the plane of the wafer.
Therefore, in order to improve the deposition of Ti and TiN into vias, apertures and contact holes (hereinafter xe2x80x9cviasxe2x80x9d), collimation sputtering techniques have been developed in the art. A known method of imparting greater directionality to the atoms reaching the wafer surface is to install a collimating filter between the source and the substrate. Such a filter might comprise a network of elongate cell-like structures, each cell having an axis perpendicular to the surface of the substrate. Atoms traveling approximately perpendicular to the substrate surface travel through the cells unimpeded. Atoms traveling at an acute angle are intercepted by a wall of one of the cells and captured. The use of a collimator allows deposition of Ti and TiN in vias with aspect ratios up to about 2 or 3. This approach, while providing good directionality, is also inefficient since much of the target material is wasted and builds up on the cell walls. The buildup of material can lead to an undesired increase in the number of particulates in the system, making it necessary to replace or clean the collimator frequently. Since most of the sputtered material does not pass through the collimator and is wasted, the deposition rate is slow and the rate of consumption of targets is high. By gradually increasing the sputter power, a practical growth rate can be obtained in forming the TiN film. However, when increasing the sputter power, it is also necessary to increase the flow rate of nitrogen. When TiN is formed on the surface of the target, the growth rate of the TiN film is reduced to less than one-third under the same sputter power as compared with the case in which Ti film is formed by the sputtering process.
On the other hand, a collimator can be used in a NNM process, in which N2 gas enters the deposition chamber towards the wafer substrate and is prevented from passing through the collimator towards the target by the flow of Ti atoms. However, in such a process, it is necessary to exactly balance and control the sputter power and the flow rates of inert Ar and N2 gases. Such control is difficult, and the Ti targets often become nitrided. In any case, when used in either a NM or a NNM mode, a collimator eventually becomes covered with deposits of Ti and TiN material. The deposited material tends to flake off the collimator, resulting in contamination of the IC substrate.
Conventional PVD sputtering is accomplished by creating at a relatively low pressure a plasma comprising, typically, an inert gas, such as argon (Ar), in the vicinity of a target cathode which is made of the material to be deposited. Positively charged plasma atoms, known as ions, then strike the target cathode, causing atoms of the target cathode to be ejected into the plasma. These target atoms then travel through the sputtering vacuum and are deposited onto the semiconductor substrate. Conventional diode PVD sputtering is inefficient and, in some instances, incapable of providing required directionality to thin films when fabricating VLSI and ULSI circuits. The plasma that is created with a standard PVD sputtering device lacks a sufficient amount of ionized target material atoms. The degree of ionization of a plasma is referred to in the art as the plasma intensity. The more intense the plasma, the greater the ability to steer and focus the plasma and, thus, impart an adequate amount of directionality to the ions in the plasma. Thus, another approach to improving the ability of a sputter source to fill grooves and vias has been to apply additional RF power to the sputtered species. This is done by applying RF power to a band of material that is the same as the target. This RF power capacitively couples into the neutral plasma, and increases the ionization of the neutral atoms. The disadvantages with this method is that the band also gets sputtered, and becomes a consumable. Additionally, the sputtering of the band can increase the amount of particles created.
To overcome the limitations of conventional PVD sputtering, the use of magnetic fields in magnetron sputtering devices has been introduced in the art. As with standard sputtering devices, a magnetron sputtering apparatus generally comprises a vacuum chamber which confines a plasma forming gas, typically an inert gas, such as argon (Ar), at a relatively low pressure, typically 3 to 5 millitorr. An electrical field (E) is then created within the vacuum chamber by applying a negative potential at the target cathode and creating an anode, typically, by means of grounding the overall sputter chamber. A magnetic field (B) is introduced into the vacuum chamber, typically in an orientation such that the field lines loop through the target cathode for the purpose of creating and confining a plasma near the target. As positive ions from the plasma strike the target, atoms are ejected from the surface of the target. The magnetic field serves to attract an electron-rich portion of the plasma in the vicinity of the target. In addition, electrons trapped about the target allow for an increase in the collisions between the neutral atoms ejected from the surface of the target and the rapidly moving electrons. By increasing the quantity of collisions, the likelihood increases that a neutral ejected target atom will be struck by a sufficiently energetic particle within the plasma, thus causing the ejected target atom to lose one or more electrons and result in an ionized atom. By increasing the quantity of ionized target atoms within the plasma, the plasma density, or intensity, increases. As the plasma intensity increases, so does the probability that further ionization of ejected target atoms will occur.
Conventional magnetron and rf-iPVD sputtering techniques are limited in their efficiency due in part to the fact that the vast majority of metal atoms ejected from the target remain neutral. Even with the use of a magnetic field to trap plasmas about the target cathode, the intensity of the plasma remains insufficient and upwards of 98% or greater of the target material atoms remain un-ionized as they travel through the sputter chamber to the substrate. As with other PVD techniques, Ti-atoms are ejected from the surface of the sputter target at a random angle and the mean-free path of travel between the target cathode and the substrate for these neutral metal atoms is reduced by random collisions with other target atoms or inert gas ions. When the predominantly neutral atoms in these plasmas do come in contact with the substrate, they characteristically do so over a wide range of angles, generally conforming to a cosine distribution. In particular, when atoms are disposed on substrate surfaces at angles less than normal, it poses significant difficulty in uniformly filling trenches and interconnect vias. U.S. Pat. No. 5,744,016, issued Apr. 28, 1998, to Yamada et al., discloses a known planar magnetron sputtering apparatus having a titanium sputter target, a collimator plate, and shield plates. The collimator is supposed to impart the requisite directionality to the sputtered material, and the shield plates are supposed to prevent formation of TiN on the collimator. The overall efficiency of such a system is very low, however, because most of the sputtered material remains un-ionized or is trapped by the shield plates.
The present invention provides a novel method in which Ti and TiN can be formed on an integrated circuit substrate in the same PVD chamber without use of either a shutter or a collimator. A method in accordance with the invention includes use of a hollow-cathode sputtering target containing titanium. The titanium-containing target is sputtered in a non-nitrided mode (xe2x80x9cNNMxe2x80x9d) in the deposition chamber of a hollow-cathode magnetron (xe2x80x9cHCMxe2x80x9d) apparatus to deposit a TiN layer on an integrated circuit substrate. Since both a Ti layer and TiN layer can be deposited on the substrate in the same deposition chamber, processing chambers in fabrication equipment are more efficiently used, and fabrication steps are simplified compared to prior art processes conducted in a plurality of chambers or done in a nitrided mode (xe2x80x9cNMxe2x80x9d). Sputtering of a HCM Ti target without use of a collimator or a shutter results in less target material being wasted than in prior art methods. The chances of flaking of material onto the IC substrate is reduced. The deposition rates of the Ti and TiN layers is faster than in apparati and methods of the prior art. For example, NNM operation in accordance with the invention provides deposition rates of 70 nm/min or more and bottom coverage greater than 30 percent while fabricating a TiN layer in a via having an aspect ratio (xe2x80x9cARxe2x80x9d) of 5:1. Also, an apparatus and a method in accordance with the present invention provide formation of high quality layers of Ti and TiN for metallizations and local interconnects having high aspect ratios. For example, a TiN film fabricated in accordance with the invention with a thickness of 100 nm has a resistivity of only about 30 xcexcohm-cm.
A method in accordance with the invention for depositing Ti and TiN on an integrated circuit substrate comprises steps of: providing a hollow cathode target having a cavity region and containing titanium; sputtering titanium from the target to form a layer containing Ti on the substrate; and sputtering titanium from the target and simultaneously flowing a nitrogen-containing gas into a deposition chamber to form a layer containing TiN on the substrate. A magnetic field is created that has a magnetic null region located between the cavity region and the substrate and which imparts directionality to Ti-ions traveling towards the substrate.
A method may further comprise: heating the substrate, preferably to a temperature in a range of from 250xc2x0 C. to 350xc2x0 C.; applying an amount of power in a range of from 20 to 36 kilowatts to the target, thereby creating a negative voltage in a range of fromxe2x88x92400 toxe2x88x92500 volts at the hollow cathode target; and applying a current not exceeding 1.0 amps to an electromagnetic coil to modify the magnetic field. In certain embodiments of the invention, the hollow target cathode and the substrate may be separated by a distance of from 215 to 240 mm. A method in accordance with the invention may be used to deposit layers of Ti and TiN having thicknesses up to several microns, the final thickness being limited by the amount of Ti target material. In typical integrated circuit fabrication, however, the thickness of a Ti layer formed is typically in a range of from 10 to 70 nm, and the thickness of a TiN layer formed is typically in a range of from 10 to 100 nm.